Program

Monday, Dec. 13th

18:00-19:30 Reception & Registration (Restaurant 3rd floor)

Tuesday, Dec. 14th

9:10-(17:30) Registration (Foyer 2nd floor)
9:30-9:40 Opening
9:40-10:40 Keynote (Conference Rooms 3 and 4)
Chair: Yutaka Ishikawa (University of Tokyo)

Towards Open Systems Dependability
Mario Tokoro
JST/CREST DEOS Project Supervisor (Sony Computer Science Laboratories, Inc.)
10:40-11:00 Break
11:00-12:30 Session I-A: Fault Injection (Conference Room 3)
Chair: Dong Tang (Oracle Corporation)

Towards Identifying the Best Variables for Failure Prediction using Injection of Realistic Software Faults
Ivano Irrera, João Durães, Marco Vieira, and Henrique Madeira (Universidade de Coimbra)

Searching Representative and Low Cost Fault Models for Intermittent Faults in Microcontrollers: A Case Study
Joaquin Gracia-Morán, Daniel Gil-Tomás, Juan-Carlos Baraza-Calvo, Luis-Jose Saiz-Adalid, and Pedro-Joaquin Gil-Vicente (Universidad Politécnica de Valencia)

Modeling the Propagation of Intermittent Hardware Faults in Programs
Layali Rashid, Karthik Pattabiraman, and Sathish Gopalakrishnan (University of British Columbia)
Session I-B: Virtual Machines (Conference Room 4)
Chair: Hiroyuki Okamura (Hiroshima University)

A Secure System-Wide Process Scheduler across Virtual Machines
Hidekazu Tadokoro (Tokyo Institute of Technology), Kenichi Kourai (Kyushu Institute of Technology), and Shigeru Chiba (Tokyo Institute of Technology)

Implementing a Hybrid Virtual Machine Monitor for Flexible and Efficient Security Mechanisms
Junya Sawazaki, Toshiyuki Maeda, and Akinori Yonezawa (University of Tokyo)

Customizing Virtual Machine with Fault Injector by Integrating with SpecC Device Model for a Software Testing Environment D-Cloud
Toshihiro Hanawa, Hitoshi Koizumi, Takayuki Banzai, Mitsuhisa Sato, Shin'ichi Miura, Tadatoshi Ishii, and Hidehisa Takamizawa (University of Tsukuba)
12:30-13:30 Lunch on Your Own
13:30-15:00 Session II-A: Chip Multi-Processors (Conference Room 3)
Chair: Toshinori Sato (Fukuoka University)

FiRot: An Efficient Crosstalk Mitigation Method for Network-on-Chips
Ahmad Patooghy, Mansour Shafaei, Seyed Ghassem Miremadi, Hajar Falahati, and Somayyeh Taheri (Sharif University of Technology)

An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors
James Weston, Masashi Imai, Tomohide Nagai (University of Tokyo), and Takashi Nanya (Canon, Inc.)

Address Remapping for Static NUCA in NoC-based Degradable Chip-Multiprocessors
Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, and Xiaowei Li (Chinese Academy of Sciences)
Session II-B: Software Reliability (Conference Room 4)
Chair: Toshiyuki Maeda (University of Tokyo)

Formal Verification of Industrial Software with Dynamic Memory Management
Sébastien Labbé (EDF Research & Development) and Arnaud Sangnier (University of Genova)

A Software Accelerated Life Testing Model
Toshiya Fujii, Tadashi Dohi, Hiroyuki Okamura (Hiroshima University), and Takaji Fujiwara (Business Cube & Partners, Inc.)

Toward a Language for Communication among Stakeholders
Yutaka Matsuno (University of Tokyo), Jin Nakazawa (Keio University), Makoto Takeyama (AIST), Midori Sugaya (Yokohama National University), and Yutaka Ishikawa (University of Tokyo)
15:00-15:30 Break
15:30-17:30 Session III-A: Real-Time/Networked Systems (Conference Room 3)
Chair: Toshihiro Hanawa (University of Tsukuba)

Sensitivity Analysis of the Minimum Task Period for Arbitrary Deadline Real-Time Systems
Fengxiang Zhang (Southwest University), Alan Burns (University of York), and Sanjoy Baruah (University of North Carolina at Chapel Hill)

An Improved Knowledge Connectivity Condition for Fault-Tolerant Consensus with Unknown Participants
Jichiang Tsai and Che-Cheng Chang (National Chung Hsing University)

A Distributed Data Replication Protocol for File Versioning with Optimal Node Assignments
Takahiko Ikeda, Mamoru Ohara, Satoshi Fukumoto, Masayuki Arai, and Kazuhiko Iwasaki (Tokyo Metropolitan University)

End-to-End Performability Analysis for Infrastructure-as-a-Service Cloud: An Interacting Stochastic Models Approach
Rahul Ghosh, Kishor Trivedi (Duke University), Vijay Naik (IBM T. J. Watson Research Center), and Dong Seong Kim (Duke University)
Session III-B: Failure Detection/Dependency (Conference Room 4)
Chair: Hidetsugu Irie (Electro-Communication University)

Deadlock Detection Scheduling for Distributed Processes in the Presence of System Failures
Akikazu Izumi, Tadashi Dohi (Hiroshima University), and Naoto Kaio (Hiroshima Shudo University)

Two Efficient Software Techniques to Detect and Correct Control-Flow Errors
Hamid Reza Zarandi, Mohammad Maghsoudloo, and Navid Khoshavi (Amirkabir University of Technology)

Analysis of Dependencies between Failures in the UNINETT IP Backbone Network
Andres J. Gonzalez, Bjarne E. Helvik (NTNU), Jon K. Hellan (UNINETT), and Pirkko Kuusela (VTT)
18:00-20:30 Banquet (Gakushikaikan)

Wednesday, Dec. 15th

9:10-(14:00) Registration (Foyer 2nd floor)
9:30-11:00 Fast Abstract (Conference Rooms 3 and 4)
Chair: Tatsuhiro Tsuchiya (Osaka University)

Composition Kernel: A Multi-Core Processor Virtualization Layer for Highly Functional Embedded Systems
Tatsuo Nakajima, Yuki Kinebuchi, Alexandre Courbot, Hiromasa Shimada, Tsung-Han Lin, and Hitoshi Mitake (Waseda University)

Optimal Inventory of Computer Repair Parts: A Fuzzy Systems Approach
Les M. Sztandera (Philadelphia University)

A Replacement Strategy for Canary Flip-Flops
Yuji Kunitake (Kyushu University), Toshinori Sato (Fukuoka University), and Hiroto Yasuura (Kyushu University)

Quantitative Evaluation of Integrity for Remote System Using the Internet
Masato Kitakami, Hiroshi Konno, Kazuteru Namba, and Hideo Ito (Chiba University)

A Speculative Byzantine Algorithm for P2P System
Yusuke Matsumoto and Hiromi Kobayashi (Tokai University)

Core-Local Memory Assisted Protection
Yuki Kinebuchi, Tatsuo Nakajima (Waseda University), Vinod Ganapathy, and Liviu Iftode (Rutgers University)

P-Bus: Programming Interface Layer for Safe OS Kernel Extensions
Hajime Fujita, Motohiko Matsuda, Toshiyuki Maeda (University of Tokyo), Shin'ichi Miura (University of Tsukuba), and Yutaka Ishikawa (University of Tokyo)

A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors
Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima (Nara Institute of Science and Technology), and Kazutoshi Kobayashi (Kyoto Institute of Technology)

Reliability Evaluation of Flip-flops Based on Probabilistic Transfer Matrices
Chengtian Ouyang, Jianhui Jiang, and Jie Xiao (Tongji University)

Automatic Static Fault Tree Analysis from System Models
Jianwen Xiang and Kazuo Yanoo (NEC Corporation)

An Asynchronous Checkpoint-Based Redundant Multithreading Architecture
Jie Yin and Jianhui Jiang (Tongji University)

A Safe Measurement-Based Worst-Case Execution Time Estimation Using Automatic Test-Data Generation
Liangliang Kong and Jianhui Jiang (Tongji University)

A Hierarchical Model for Reliability Analysis of Sensor Networks
Dong Seong Kim, Rahul Ghosh, and Kishor S. Trivedi (Duke University)

The Performance Analysis and Hardware Acceleration of Crypto-Computations for Enhanced Security
Jed Kao-Tung Chang (University of California), Chen Liu (Florida International University), Shaoshan Liu (Microsoft Corp.), and Jean-Luc Gaudiot (University of California)

Formal Validation and Requirements Management Based on the Jackson's Reference Model for Requirements and Specifications
Takashi Kitamura, Keishi Okamoto, and Makoto Takeyama (AIST)
11:00-13:00 Research Exhibition (Conference Room 2)

A Composition Kernel: A Software Infrastructure for Building Complex Embedded Systems
Tatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, and Tsung-Han Lin (Waseda University)

Dependability Measurements and Evaluation Tool: DS-Bench/D-Cloud
Yutaka Ishikawa (University of Tokyo), Mitsuhisa Sato, Toshihiro Hanawa (University of Tsukuba), Hajime Fujita (University of Tokyo), Takayuki Banzai, Hitoshi Koizumi, and Shin'ichi Miura (University of Tsukuba)

Dependable Scripting Language: Use Case of Evidence Management
Kimio Kuramitsu (Yokohama National University)

Formal Verification Tools for Systems Software
Toshiyuki Maeda, Motohiko Matsuda, Hajime Fujita (University of Tokyo), Shin'ich Miura (University of Tsukuba), and Yutaka Ishikawa (University of Tokyo)

Dependable Power-efficient File Server
Hajime Fujita and Yutaka Ishikawa (University of Tokyo)

DMR mode of SmartCore system
Shimpei Sato, Shinya Takamaeda, and Kenji Kise (Tokyo Institute of Technology)

Dependable Network-on-Chip Platform
Daihan Wang, Chammika Mannakkara, Vijay Holimath and Tomohiro Yoneda (National Institute of Informatics)

Yet Another Taint Mode for PHP
Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai (University of Tokyo)

Dependable Responsive Processor for Distributed Real-Time Systems
Kazutoshi Suito (Keio University)
13:00-14:00 Lunch on Your Own
14:00-15:00 Invited Talk (Conference Rooms 3 and 4)
Chair: Tomohiro Yoneda (National Institute of Informatics)

Dependable E-Payment System in Japan -- Dependability, Accountability and Security
Tadashi Morita
Sony Corporation
15:00-15:30 Break
15:30-17:30 Session IV-A: Architectures (Conference Room 3)
Chair: Nobuyasu Kanekawa (Hitachi Ltd.)

System-Level Vulnerability Estimation for Data Caches
Alireza Haghdoost, Hossein Asadi (Sharif University of Technology), and Amirali Baniasadi (University of Victoria)

Loris - A Dependable, Modular File-Based Storage Stack
Raja Appuswamy, David C. van Moolenbroek, and Andrew S. Tanenbaum (Vrije Universiteit)

Design and Implementation of a Fault Tolerant Single IP Address Cluster
Jun Kato, Hajime Fujita, and Yutaka Ishikawa (University of Tokyo)

On the Reliability of Cascaded TMR Systems
Masashi Hamamatsu, Tatsuhiro Tsuchiya, and Tohru Kikuno (Osaka University)
Session IV-B: System Security (Conference Room 4)
Chair: Hiroshi Yamada (Keio University)

A Learning-Based Approach to Secure Web Services from SQL/XPath Injection Attacks
Nuno Laranjeiro, Marco Vieira, and Henrique Madeira (University of Coimbra)

Estimating Computer Virus Propagation Based on Markovian Arrival Processes
Hiroyuki Okamura and Tadashi Dohi (Hiroshima University)

Dynamic Multilayer Routing to Achieve Location-Hiding
Hakem Beitollahi and Geert Deconinck (K. U. Leuven)

Sequential Frequency Vector Based System Call Anomaly Detection
Ying Wu, Jianhui Jiang, and Liangliang Kong (Tongji University)
17:30- Closing (Conference Room 3)

Keynote Speaker

Dr. Mario Tokoro, JST/CREST DEOS Project Supervisor (Sony Computer Science Laboratories, Inc.)

Invited Speaker

Mr. Tadashi Morita, General Manager, Sony Corporation

Research Exhibition

A Composition Kernel: A Software Infrastructure for Building Complex Embedded Systems
Tatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, and Tsung-Han Lin (Waseda University)
Abstract:
A virtualization layer makes it possible to compose multiple functionalities on a multi-core processor with the minimum modification of OS kernels and applications. A multi-core processor is a good candidate to compose various software independently developed for dedicated processors into one multi-core processor to reduce both the hardware and development cost. In this demonstration, we present SPUMONE, which is a virtualization layer suitable for developing multi-core processor based-information appliances. SPUMONE offers several features to increase dependability of systems, and the features enable us to develop high reliable embedded systems without increasing overhead.

Dependability Measurements and Evaluation Tool: DS-Bench/D-Cloud
Yutaka Ishikawa (University of Tokyo), Mitsuhisa Sato, Toshihiro Hanawa (University of Tsukuba), Hajime Fujita (University of Tokyo), Takayuki Banzai, Hitoshi Koizumi, and Shin'ichi Miura (University of Tsukuba)
Abstract:
The DS-Bench/D-Cloud is a tool to execute dependability benchmarks in order to measure availability, reliability, performance, and power consumption which are evidences required by D-Case at the design and test phases. In the DS-Bench/D-Cloud, a virtual machine is used to simulate hardware faults. If a device is specified by the SpecC hardware description language, a fault of the device can be simulated with the virtual machine. The actual target machine is used for testing a software bug related to timing, and is used for power down and network failure which can be produced using the specific equipment. A Cloud environment is provided to perform dependability benchmarks in parallel for shorting the testing phase. We will exhibit DS-Bench and D-Cloud environment, and demonstrate examples of Dependability Benchmarks using DS-Bench and examples of software testing scenarios using D-Cloud.

Dependable Scripting Language: Use Case of Evidence Management
Kimio Kuramitsu (Yokohama National University)
Abstract:
Recently, scripting languages have become an integral means to develop application software, as well as to configure system operations. However language supports for dependability issues have been largely ignored. We address these issues by designing a new dependable scripting language, named Konoha. Dependability issues supported in Konoha ranges from static type safety to runtime error recovery. This demonstration will show the implementation status of Konoha by using an evidence-based dependability management scenario co-worked with the JST/CREST DEOS Project.

Formal Verification Tools for Systems Software
Toshiyuki Maeda, Motohiko Matsuda, Hajime Fujita (University of Tokyo), Shin'ich Miura (University of Tsukuba), and Yutaka Ishikawa (University of Tokyo)
Abstract:
We are developing formal program development approaches and tools for detecting defects in systems software including operating system kernels, thereby to contribute to achieving systems software dependability. More specifically, we have been developing approaches and tools for avoiding bugs in programs and supporting continuous handling of unexpected system failures. In order to achieve the objectives mentioned above, we have been researching and developing two formal methods, model checking and type checking, for formal verification on C programs which is frequently used for systems software. Model checking verifies relatively complex safety properties. This takes rather a long time. On the other hand, type checking verifies relatively simple safety properties. This can be done in a short time. We will report current status of our work by presenting demonstrations.

Dependable Power-efficient File Server
Hajime Fujita and Yutaka Ishikawa (University of Tokyo)
Abstract:
We demonstrate a dependable and power-efficient WebDAV file server. This file server consists of multiple server nodes to make improvements on performance and availability. However, the server shows a single system image to clients so that the clients can access to the server as if it were a regular single file server. Files written by clients are stored in multiple server nodes in order to ensure that files are not lost even when a part of server nodes crashes Several requests are distributed across multiple nodes to improve overall throughput. The server has a single IP address accessible from clients. This makes it possible for the server to add or remove nodes transparently to clients, and therefore the number of active server nodes can be adjusted dynamically depending on required performance, in order to reduce unnecessary power consumption.

DMR mode of SmartCore system
Shimpei Sato, Shinya Takamaeda, and Kenji Kise (Tokyo Institute of Technology)
Abstract:
The SmartCore system aims high dependability and high performance on many-core processors. The unique point of this system is using on-chip network routers. The Router of SmartCore system, called the multi-function router, have various functions, such as copying packets, in addition to routing packets. By these functions, SmartCore system utilizes the redundant modules on a chip and achieves a high dependability or high performance of many-core processors. In this exhibit, we demonstrate a DMR mode of SmartCore system. To realize this mode, we add three functions to the router: copying packets, changing the destination of packets, and rendezvousing and comparing two packets from different nodes. In this mode, two cores are coupled to redundantly execute a thread, and the multi-function router detects faults in packets from these cores. From the software simulation of this system, we found that the overhead of redundant execution is small. And, we verified the router detects faults in packets using FPGAs.

Dependable Network-on-Chip Platform
Daihan Wang, Chammika Mannakkara, Vijay Holimath and Tomohiro Yoneda (National Institute of Informatics)
Abstract:
In order to obtain large and complex VLSI systems using advanced semiconductor process technologies, problems of how to increase utilization of collected many cores and how to tolerate delay variation due to process variation, delay faults caused during operation, changes of environmental parameters, and so on should be solved. We are trying to develop several core technologies to overcome those problems and propose a design methodology to construct highly dependable, adaptable, and efficient network-on-chip platform. In this exhibit, we will demonstrate that some concrete automotive applications are performed on our latest prototype NoC platform.

Yet Another Taint Mode for PHP
Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai (University of Tokyo)
Abstract:
Now attacks by exploiting security vulnerabilities such as SQL injection and cross-site scripting (XSS) are becoming seriously. Dynamic Taint Propagation (DTP) has been proposed as a promising platform for detecting a wide range of injection attacks. The idea behind DTP is to tag data from untrusted sources as tainted, dynamically propagate tainted information from sources to destinations operations and check whether the tainted data is an attack or not. Though DTPs are considered to have potential to root out script injection attacks, current systems still suffer from table reference trade-off between false positives and negatives. Therefore, we proposed String- Wise Information Flow Tracking (SWIFT), which provided a better accuracy on detecting script injection attacks. This year, we started to implement SWIFT on PHP. In our live demonstration, we plan to show that tainted information is correctly propagated through real-world PHP web applications with known vulnerabilities and original PHP programs.

Dependable Responsive Processor for Distributed Real-Time Systems
Kazutoshi Suito (Keio University)
Abstract:
We have been researching and developing a generic technology to realize a dependable and practical VLSI system for distributed real-time systems such as a humanoid robot by co-designing SoC (System-on-Chip) and SiP (System-in-Package). Distributed real-time systems have been becoming more popular and important in recent years. The key technologies of the real-time systems are real-time inter-node communications, a real-time processing architecture, real-time operating systems, and the dependability for them. To realize practical dependable distributed real-time systems, we have been designing and implementing a Dependable Responsive Multi-Threaded Processor (D-RMTP). The D-RMTP is a system-on-a-chip (SoC) that integrates a real-time processing core (RMT Processing Unit (RMT PU)), Responsive Link (ISO/IEC 24740:2008) for a real-time inter-node communication, and various I/O peripherals including SpaceWire, IEEE1394, PCI-X, Ethernet, PWM generators, SPI for ADCs/DACs, etc. The RMT PU executes eight prioritized threads simultaneously by using a prioritized SMT architecture. An IPC control scheme and a tracing mechanism are also designed and implemented on D-RMTP to improve the dependability. Responsive Link provides a dependable real-time inter-node communication, so that Responsive Link has the priority-based packet-overtaking function at each node and a robust error correction function. We will demonstrate a real-time processing, a real-time communication, and the dependability for them using the D-RMTP.